Comparative analysis of OpenCL and RTL for sort-merge primitives on FPGA
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
As a result of recent improvements in FPGA technology, their benefits for highly efficient data processing pipelines are becoming more and more apparent. However, traditional RTL methods for programming FPGAs require knowledge of digital design and hardware description languages. OpenCL™ provides software developers with a C-based platform for implementing their applications without deep knowledge of digital design. In this paper, we conduct a comparative analysis of OpenCL and RTL-based implementations of a novel heapsort with merging sorted runs. In particular, we quantitatively compare their performance, FPGA resource utilization, and development effort. Our results show that while requiring comparable development effort, RTL implementations of critical primitives used in the algorithm achieve 4X better performance while using half as much the FPGA resources.
Details
Original language | English |
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Title of host publication | DaMoN '20: Proceedings of the 16th International Workshop on Data Management on New Hardware |
Publisher | Association for Computing Machinery (ACM), New York |
Pages | 11:1-11:7 |
Number of pages | 7 |
ISBN (print) | 978-1-4503-8024-9 |
Publication status | Published - 15 Jun 2020 |
Peer-reviewed | Yes |
Publication series
Series | MOD: International Conference on Management of Data (DaMoN) |
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ISSN | 0730-8078 |
Conference
Title | 16th International Workshop on Data Management on New Hardware, DaMoN 2020 |
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Duration | 15 June 2020 |
City | Portland |
Country | United States of America |
External IDs
Scopus | 85087631253 |
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ORCID | /0000-0001-8107-2775/work/142253578 |
Keywords
ASJC Scopus subject areas
Keywords
- external sorting, FPGA, heapsort, high level synthesis, Intel OpenCL, RTL, sorting