Blocks: challenging SIMDs and VLIWs with a reconfigurable architecture

Research output: Contribution to journalResearch articleContributedpeer-review


Demand for coarse grain reconfigurable architectures (CGRAs) has significantly increased in recent years as architectures need to be both energy efficient and flexible. However, most CGRAs are optimized for performance instead of energy efficiency. In this work a novel paradigm for reconfigurable architectures, Blocks, is presented. Blocks uses two separate circuit-switched networks, one for control and one for the data-path. This enables run-time construction of energy-efficient application-specific VLIW-SIMD processors on a reconfigurable fabric. Its energy efficiency is demonstrated by comparing Blocks to four reference architectures, a VLIW, an SIMD, a commercial low-power microprocessor, and a traditional CGRA. All comparisons are based on commercial low-power 40nm CMOS layout, including memories. Results show that Blocks can achieve a mean total energy reduction of 2.05x, 1.84x, 8.01x, 1.22x over a VLIW, an SIMD, an energy-efficient microprocessor and a traditional CGRA respectively. At the same time, Blocks delivers equal or higher performance per area due to its ability to adapt to applications by reconfiguration.


Original languageEnglish
Pages (from-to)2915 - 2928
Number of pages14
JournalIEEE transactions on computer-aided design of integrated circuits and systems
Issue number9
Publication statusPublished - 15 Oct 2021


Research priority areas of TU Dresden

Sustainable Development Goals


  • CGRA, Computer architecture, Energy Efficiency., Fabrics, Field programmable gate arrays, Performance evaluation, Program processors, Reconfigurable Architecture, Registers, VLIW