The increasing use of FPGAs necessitates energy-efficient solutions, particularly for battery-powered applications. While power dissipation is often perceived as a hardware issue, it can be mitigated through power-saving techniques such as dynamic voltage and frequency scaling and clock gating. In real-time systems, these strategies must reduce power consumption and meet strict timing requirements to avoid deadline violations. However, hardware constraints and variability in execution times complicate their implementation, particularly in multi-core systems where task dependencies and inter-processor communication introduce delays and unpredictability. Real-time Operating Systems (RTOSs) manage task execution using scheduling algorithms, periodically checking task queues during context switches. Incoming messages trigger sporadic tasks that the RTOS must prioritize immediately, while regular tasks are executed, or power-saving strategies are applied during idle phases. Handling these diverse tasks in multi-core systems adds complexity, making it challenging to balance between predictability, energy efficiency, and system performance. This work introduces a heterogeneous multi-core architecture that integrates power-aware task scheduling algorithms, such as the Look-Ahead algorithm or Race-to-Idle strategy, to optimize power consumption while addressing task dependencies and inter-core communication. A hardware-based task scheduler improves scheduling performance and predictability, while tasks leverage the reconfigurable capabilities of FPGAs and are executed as hardware accelerators to further enhance energy efficiency. The experimental results demonstrate an improvement in scheduling performance of 64.91% and energy efficiency of 92% compared to a baseline without power optimization, highlighting the effectiveness of the proposed approach.