ARTNoCs: An evaluation framework for hardware architectures of real-time NoCs

Research output: Contribution to book/conference proceedings/anthology/reportConference contributionContributedpeer-review

Contributors

  • Salma Hesham - , German University in Cairo, Ruhr University Bochum (Author)
  • Diana Gohringer - , Ruhr University Bochum (Author)
  • Mohamed Abd El Ghany - , German University in Cairo, Technische Universität Darmstadt (Author)

Abstract

NoC-based MPSoCs are the fitting platform for the requirements of embedded and cyber physical systems. A significant expanse of these systems abides by real-time constraints which further add to the NoC design challenges. Several architectural solutions are presented in the literature targeting real-time NoCs, also referred to as quality of service (QoS) NoCs, however, they lack a common evaluation platform and performance criteria. In this paper, ARTNoCs is proposed as a hardware evaluation framework for real-time NoC architectures in a 2D mesh platform. The proposed framework supports different QoS router architectures in terms of switching control, ports structure, routing algorithm, flow-control and node latency. The framework offers a common hardware evaluation platform for the different router architectures over both FPGA and ASIC design flows, in addition to the latency and real-time performance evaluation under specified traffic scenarios. ARTNoCs is the first framework targeting real-time NoCs allowing the designer to compare and contrast different QoS router architectures on a reliable evaluation platform.

Details

Original languageEnglish
Title of host publicationProceedings - 2016 IEEE 30th International Parallel and Distributed Processing Symposium, IPDPS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages259-264
Number of pages6
ISBN (electronic)9781509021406
Publication statusPublished - 18 Jul 2016
Peer-reviewedYes
Externally publishedYes

Publication series

SeriesProceedings - 2016 IEEE 30th International Parallel and Distributed Processing Symposium, IPDPS 2016

Conference

Title30th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2016
Duration23 - 27 May 2016
CityChicago
CountryUnited States of America

External IDs

ORCID /0000-0003-2571-8441/work/159607541

Keywords

ASJC Scopus subject areas

Keywords

  • MPSoC, Networks-on-Chip, Quality-of-Service, Real-time