Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators.
Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed › peer-review
Contributors
Details
| Original language | Undefined |
|---|---|
| Title of host publication | DAC |
| Pages | 159:1-159:6 |
| Number of pages | 6 |
| Publication status | Published - 2018 |
| Peer-reviewed | Yes |
External IDs
| Scopus | 85053690223 |
|---|