Area-Optimized Accurate and Approximate Softcore Signed Multiplier Architectures.
Research output: Contribution to journal › Research article › Contributed › peer-review
Contributors
Abstract
Multiplication is one of the most extensively used arithmetic operations in a wide range of applications. In order to provide resource-efficient and high-performance multipliers, previous works have proposed different designs of accurate and approximate multipliers - mainly for ASIC-based systems. However, the architectural differences between ASICs- and FPGA-based systems limit the effectiveness of these multipliers for FPGA-based systems. Moreover, most of these multiplier designs are valid only for unsigned numbers. To bridge this gap, we propose a novel implementation technique for designing resource-efficient and low-power accurate and approximate signed multipliers which are optimized for FPGA-based systems. Compared to Vivado's area-optimized multiplier IPs, the designs obtained using our proposed technique occupy 47 to 63 percent less area (Lookup Tables). To accelerate further research in this direction and reproduce the presented results, the RTL and behavioral models of our proposed methodology are available as an open-source library.11.Online. [Available]: https://cfaed.tu-dresden.de/pd-downloads.
Details
Original language | English |
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Article number | 9072581 |
Pages (from-to) | 384-392 |
Number of pages | 9 |
Journal | IEEE transactions on computers |
Volume | 70 |
Issue number | 3 |
Publication status | Published - 1 Mar 2021 |
Peer-reviewed | Yes |
External IDs
Scopus | 85083809499 |
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Keywords
Research priority areas of TU Dresden
Sustainable Development Goals
ASJC Scopus subject areas
Keywords
- accurate, approximate computing, booth's multiplication, energy efficiency, FPGA, Signed multiplier