Analysis of process traces for mapping dynamic KPN applications to MPSoCs

Research output: Contribution to book/conference proceedings/anthology/reportConference contributionContributedpeer-review

Abstract

Current approaches for mapping Kahn Process Networks (KPN) and Dynamic Data Flow (DDF) applications rely on assumptions on the program behavior specific to an execution. Thus, a near-optimal mapping, computed for a given input data set, may become sub-optimal at run-time. This happens when a different data set induces a significantly different behavior. We address this problem by leveraging inherent mathematical structures of the dataflow models and the hardware architectures. On the side of the dataflow models, we rely on the monoid structure of histories and traces. This structure help us formalize the behavior of multiple executions of a given dynamic application. By defining metrics we have a formal framework for comparing the executions. On the side of the hardware, we take advantage of symmetries in the architecture to reduce the search space for the mapping problem. We evaluate our implementation on execution variations of a randomly-generated KPN application and on a low-variation JPEG encoder benchmark. Using the described methods we show that trace differences are not sufficient for characterizing performance losses. Additionally, using platform symmetries we manage to reduce the design space in the experiments by two orders of magnitude.

Details

Original languageEnglish
Title of host publicationSystem Level Design from HW/SW to Memory for Embedded Systems - 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Proceedings
EditorsMarco Aurelio Wehrmeister, Gunar Schirner, Mohammad Abdullah Al Faruque, Achim Rettberg, Marcelo Gotz
PublisherSpringer Verlag, New York
Pages116-127
Number of pages12
ISBN (print)9783319900223
Publication statusPublished - 2017
Peer-reviewedYes

Publication series

SeriesIFIP Advances in Information and Communication Technology
Volume523
ISSN1868-4238

Conference

Title5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015
Duration3 - 6 November 2015
CityFoz do Iguaçu
CountryBrazil

External IDs

ORCID /0000-0002-5007-445X/work/141545552