An Evaluation of the Equivalent Inverter Modeling Approach

Research output: Contribution to journalResearch articleContributedpeer-review

Contributors

  • Ioannis Messaris - , Chair of Fundamentals of Electrical Engineering (Author)
  • Christina Galani - , Aristotle University of Thessaloniki (Author)
  • Maria Ntogramatzi - , Aristotle University of Thessaloniki (Author)
  • Nikolaos Karagiorgos - , Aristotle University of Thessaloniki (Author)
  • Panagiotis Chaourani - , Aristotle University of Thessaloniki (Author)
  • Andreas Tzormpatzoglou - , Aristotle University of Thessaloniki (Author)
  • Sotirios Goudos - , Aristotle University of Thessaloniki (Author)
  • Spyridon Nikolaidis - , Aristotle University of Thessaloniki (Author)

Abstract

Accurate modeling of CMOS logic gates for timing and power characterization is a very important task in integrated circuits technology since it facilitates significantly the design phase. Parametric models provide flexibility in determining the circuit performance in various design corners. However, the direct analysis of a complex CMOS gate aiming in an analytical and parametric model is a difficult and cumbersome task. An alternative way to model these gates is by using the equivalent inverter approach. According to this, an inverter with appropriate transistor widths is defined in order to present the same response with the complex gate it models. The challenge with this approach is to propose a simple method to predict the appropriate transistor widths of the equivalent inverter. Then, an analytical model for the CMOS inverter can be used to provide estimates for the complex gates. In this paper, a macro-modeling method is proposed for determining the transistor widths of the equivalent inverter and a technique for providing parametric expressions for these widths in terms of input transition time, output capacitive load, initial transistor width, supply voltage and temperature. A tool is developed to provide timing and power characterizations for the cells of a digital cell library, much faster than conventional numerical circuit simulators. The results prove the efficiency of the equivalent inverter approach in modeling complex gates.

Details

Original languageEnglish
Pages (from-to)2665-2693
Number of pages29
JournalCircuits, Systems, and Signal Processing
Volume37
Issue number7
Publication statusPublished - 1 Jul 2018
Peer-reviewedYes

Keywords

ASJC Scopus subject areas

Keywords

  • CCS compatible, CMOS gate modeling, Equivalent inverter, Simulation, Timing/power characterization