An efficient 70 GHz divide-by-4 CMOS frequency divider employing low threshold devices

Research output: Contribution to journalResearch articleContributedpeer-review


The idea to use a lower threshold, but slightly slower transistor over the fastest transistor type for large-signal circuits is presented with experimental verification for a compact divide-by-4 true single phase clock (TSPC) frequency divider. The use of the lowest threshold PMOS devices resulted in self-resonance frequencies of 41.7, 56, and 60 GHz at supply voltages of 0.5, 0.8 and 0.9 V, respectively. Compared to a divider of the same architecture in the same technology, but with higher threshold voltage devices, this corresponds to improvements of 67%, 33% and 27%, respectively. Power consumptions of 26 and 355 (Formula presented.) W were measured for a 20 GHz and a 70 GHz input signal for supply voltages of 0.5 and 0.9 V, respectively. The best knowledge of the authors, these results are the best reported to date for TSPC divider architecture, and they compete with state of the art for inductorless current-mode logic dividers.


Original languageEnglish
Pages (from-to)545-547
Number of pages3
JournalElectronics Letters
Issue number14
Publication statusPublished - Jul 2021


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