A low-power 8 bit single-core successive approximation register (SAR) analog-to-digital converter (ADC) with a sampling rate of up to 1.25 GS/s based on alternating comparators is studied. To prove the concept, the circuit is implemented in a 22 nm fully-depleted silicon-on-insulator (FDSOI) technology. Key power dissipating factors are explored considering the high sampling rate. A scheme is investigated, where each memory cell activates the second next memory cell to relax the speed requirement and allow for power savings compared to conventional approaches. A modified, non-overlapped signaling is used in the driver for the capacitive digital-to-analog converter (CDAC) to reduce a direct-path current and to ease the reference buffer design. Measurements show an effective number of bits (ENOB) of 6.86 bit near the Nyquist frequency. A power consumption of 1.73mW is measured, leading to the best Walden figure-of-merit of 11.9 fJ/c.-step for a single-core SAR ADC above 1 GS/s.