The rapid expansion of the Internet of Things, wireless sensor networks, and robotics applications have established embedded systems as a fundamental component of modern computing. Despite this growth, optimizing power consumption and computing resources remains critical. Traditional embedded platforms often struggle with fixed hardware configurations that limit their adaptability and efficiency. To address these issues, this paper presents a novel adaptive processor architecture based on RISC-V ISA which introduces reconfigurable execution regions capable of supporting mixed-precision operations (16/8/4-bit). These reconfigurable execution regions execute and continuously adapt to varying precision and operational demands triggered by custom RISC-V instructions that activate the desired region at specific precision levels. The reconfiguration process is managed through dynamic function exchange (DFX) targeting AMD/Xilinx XCZU7EV FPGA device. The evaluation demonstrates that the modified core efficiently utilizes FPGA resources, with 6,396 LUTs and 2,679 FFs allocated, and operates with a dynamic power consumption of 24 mW at 50 MHz. The reconfiguration time is 76 ms for each reconfiguration execution region, incorporating the overhead required for reconfiguration management and control. These results highlight the core's potential to allow the realization of RISC-V-based reconfigurable cores without degrading performance and energy efficiency for embedded applications.