AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors

Research output: Contribution to journalResearch articleContributedpeer-review

Contributors

Abstract

Tile-based many-core architectures are extensively used in modern system-on-chip designs to achieve scalable computing performance with adequate energy efficiency. Heterogeneity is the key element to boost computing performance and keep energy consumption under certain limits for several application domains. However, the steady increase of using many custom heterogeneous tiles leads to an expansion in design and integration cost with limited tiles re-usability. The recent widespread of open-source RISC-V ISA provides the potential to develop modular compute units that can be used for many application domains with high reduction in non-recurring engineering costs. The motivation of this work is to bring design modularity and adaptability features for heterogeneous tile-based many-core architectures by increasing their flexibility to realize different many-core configurations with less design time and costs. In this work, AGILER is proposed as an adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular and adaptable heterogeneous multi-/single-core compute tiles that supports 32-/64-bit RISC-V ISAs with different memory hierarchies. Inter-tile communication is developed based on a scalable network-on-chip architecture to achieve a high degree of system scalability. AGILER supports run-time adaptation through a custom internal reconfiguration manager for dynamic and partial reconfiguration over Xilinx FPGAs. Evaluation results demonstrate that the proposed architecture features a scalable computing performance up to 685 MOPS for 8\times 32 -bit tiles and 316 MOPS for 8\times 64 -bit tiles with a scalable memory bandwidth up to 7.4 GB/s. AGILER is evaluated on Xilinx Virtex Ultrascale+ FPGA with a maximum reconfiguration time of 38.1 ms for a single compute tile.

Details

Original languageEnglish
Pages (from-to)43895-43913
Number of pages19
JournalIEEE Access
Volume10
Publication statusPublished - 18 Apr 2022
Peer-reviewedYes

External IDs

unpaywall 10.1109/access.2022.3168686
Scopus 85129219203
Mendeley df0701d0-f890-34ad-b534-668156c15c00
dblp journals/access/KamaleldinG22

Keywords

Sustainable Development Goals

Keywords

  • Many-core architecture, RISC-V, field programmable gate array (FPGA), network-on-chip (NoC), parallel computing, reconfigurable computing