This paper presents a bang-bang phase detector (PD) and decision circuit specifically designed for random data recovery at 25 Gbps. To prove the concept, the circuits are implemented in 130 nm SiGe BiCMOS technology. The design addresses the challenge of removing static phase offsets between clock and data paths through careful layout considerations and current variations. Improved phase detection accuracy is achieved by optimizing and minimizing challenges such as signal path delays and process variations. The study includes detailed comparisons between pre-layout and post-layout simulations to demonstrate the reduction in phase offsets achieved through layout optimization. The adverse effects of process variations are removed by adjusting the bias current during measurements, resulting in a significant phase offset adjustment range of 85°. Additionally, the PD gain can be adjusted, providing flexibility in optimizing its performance for different operating conditions. This work advances the state-of-the-art in the design of PDs for high-speed data recovery systems for modern communication applications.