Embedded systems usually integrate multiple Pro-cessing Elements (PEs) on a single chip. Various PEs are con-nected to the same Tightly Coupled Memory (TCM) to increase the area and energy efficiency. However, memory sharing comes at the cost of conflicts resulting in performance degradation. To counteract this issue, Access Interval Prediction (AIP) has been introduced in the literature to predict the interval between two memory accesses. State-of-the-art AIP units are based on predictors proposed for branch prediction, such as TAgged GEometric (TAGE). This work shows for the first time that several types of neural networks are suitable for AIP as well. By treating AIP as a classification problem, we can continue to decrease the error rate compared to the TAGE predictor. For example, Vision Transformer (ViT) networks reduce the average error rate by over one-third to 2.1 percent. Through our investigation, we demonstrate that offline training alone is sufficient since the memory access traces contain the same repetitive patterns independent from the input parameters of the program run.