Field Programmable Gate Arrays (FPGAs) have increasingly become important technical support for complex computing requirements in the embedded domain due to their configurability and high performance. FPGA virtualization enables multiple tasks or operating systems to share hardware resources effectively. However, the possibility of resource-sharing also brings potential computing security risks. Especially when multiple software tasks share limited hardware resources such as accelerators with the same function, access control of hardware resources and security analysis are essential. This work explores the security robustness of a system consisting of a hardware-level scheduler that can manage hardware tasks in both spatial and temporal dimensions. It employs a lightweight threat model and systematically emulates attacks. The result shows that the hardware-level scheduler with access control successfully mitigates tampering threats and prevents denial of service attacks. These advantages demonstrate the significant potential of hardware-level access control and scheduling for embedded domains, enhancing computational efficiency and security robustness.