Current microcontroller units (MCUs) incorporate 2 complex clock systems that span a huge configuration space. The 3 impact of individual low-level clock configurations for minimizing 4 energy has not come into focus, yet. In this paper, we present 5 a generic power model of system clocks and a method to semi6 empirically parametrize it for a given platform. Following a fully 7 automated measurement and optimization process, we derive 8 results for two platforms of largely diverse clock architectures. 9 Our empirical evaluation shows successful fits of the ground10 truth power measurements for both platforms. With the lean 11 platform models at hand, we are able to (i) predict the power 12 consumption for all configurations of the clock tree, which allows 13 for (ii) static energy optimization at development time and (iii) 14 dynamic optimization of a Dynamic Voltage and Frequency 15 Scaling (DVFS) service during runtime. The model also allows 16 (iv) to quantify the hidden energy consumption of internal clock 17 nodes.