A multi-stage leakage aware resource management technique for reconfigurable architectures
Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Shrinking size of transistors has enabled us to integrate more and more logic elements into FPGA chips leading to higher computing power. However, it also brings serious concern to the leakage power dissipation of the FPGA devices. One of the major reasons for leakage power dissipation in FPGA is the utilization of prefetching technique to minimize the reconfiguration overhead (delay) in Partially Reconfigurable (PR) FPGAs. This technique creates delays between the reconfiguration and execution parts of a task, which may lead up to 44% leakage power of FPGA since the SRAM-cells containing reconfiguration information cannot be powered down. In this work, a resource management approach containing scheduling, placement and post-placement stages has been proposed to address the aforementioned issue. In scheduling stage, a leakage-aware cost function is derived to cope with the leakage power. The placement stage uses a cost function that allows designers to decide a trade-off between performance and leakage-saving. The post-placement stage employs a heuristic approach and shows further improvements. Experiments show that our approach can achieve large leakage savings for both synthetic and real life applications with acceptable extended deadline. Furthermore, different variants of the proposed approach can reduce leakage power by 40-65% when compared to a performance-driven approach and by 15-43% when compared to state-of-the-art works.
Details
Original language | English |
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Title of host publication | GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSI |
Publisher | Association for Computing Machinery (ACM), New York |
Pages | 63-68 |
Number of pages | 6 |
ISBN (electronic) | 978-1-4503-2816-6 |
Publication status | Published - 2014 |
Peer-reviewed | Yes |
Externally published | Yes |
Publication series
Series | GLSVLSI: Great Lakes Symposium on VLSI |
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Conference
Title | 24th Great Lakes Symposium on VLSI, GLSVLSI 2014 |
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Duration | 21 - 23 May 2014 |
City | Houston, TX |
Country | United States of America |
Keywords
Research priority areas of TU Dresden
ASJC Scopus subject areas
Keywords
- fpga, leakage aware, resource management