A Flexible Mixed-Mesh FPGA Cluster Architecture for High Speed Computing
Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed › peer-review
Contributors
Abstract
This paper focuses on integrating multiple FPGAs for High-Performance Computing (HPC) applications with a priority on computational capability and reliability. It introduces a reliable inter-FPGA cluster architecture, detailing experimental results of FPGA communication layer performance and hardware management using FreeRTOS on a TMR Microblaze processor. The communication layer features a hardware core for inter-FPGA communication performance, evaluated on a multi-FPGA cluster testbed. Results demonstrate high-speed data transfer and fault tolerance. The hardware manager enhances system flexibility, enabling dynamic task scheduling for hardware accelerators. The paper’s benchmark application is an image-processing pipeline, showing practical applicability with data throughput exceeding 67.4 Gb/s and low latency of 288 ns.
Details
Original language | English |
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Title of host publication | Applied Reconfigurable Computing. Architectures, Tools, and Applications - 20th International Symposium, ARC 2024, Proceedings |
Editors | Iouliia Skliarova, Piedad Brox Jiménez, Mário Véstias, Pedro C. Diniz |
Pages | 267-281 |
Number of pages | 15 |
ISBN (electronic) | 978-3-031-55673-9 |
Publication status | Published - 2024 |
Peer-reviewed | Yes |
Publication series
Series | Lecture Notes in Computer Science |
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Volume | 14553 |
ISSN | 0302-9743 |
External IDs
ORCID | /0000-0003-2571-8441/work/156812066 |
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ORCID | /0000-0001-5005-0928/work/156812408 |
Scopus | 85188747004 |
ORCID | /0000-0002-6311-3251/work/157319088 |
Mendeley | 7ab71b1d-9cfc-370a-9aeb-0400ab8afea5 |
Keywords
Keywords
- FPGA cluster, radiation hardening, FPGA-FPGA communication, parallel processing