A flexible inexact TMR technique for SRAM-based FPGAs
Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Single Event Upsets (SEUs) inadvertently change the logic memory and thereby the configuration of the Field Programmable Gate Arrays (FPGAs), leading to their incorrect functioning. Traditional methods to tolerate such faults include Triple Modular Redundancy (TMR). However, such method has a high overhead in terms of power and area. Moreover, the inexact methods used in ASICs to overcome this problem are not efficient when applied in FPGAs. Therefore, this paper proposes a novel technique based on heuristic to tolerate faults in SRAM-based FPGAs by using inexact modules in conjunction with TMR, thus reducing the area and power overhead of the design. Experiments run on various MCNC benchmark circuits show the accuracy of the proposed technique. They also show that the design solutions found through this technique only differ 0.52% on average from the optimal ones and savings up to 84.4% in terms of computation time can be reached on average.
Details
Original language | English |
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Title of host publication | 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) |
Publisher | IEEE, New York [u. a.] |
Pages | 810-813 |
Number of pages | 4 |
ISBN (electronic) | 978-3-9815-3707-9 |
Publication status | Published - 25 Apr 2016 |
Peer-reviewed | Yes |
Publication series
Series | Design, Automation and Test in Europe Conference and Exhibition (DATE) |
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ISSN | 1530-1591 |
Conference
Title | 2016 Design, Automation and Test in Europe Conference and Exhibition |
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Abbreviated title | DATE 2016 |
Conference number | 19 |
Duration | 14 - 18 March 2016 |
Website | |
Location | International Congress Center Dresden |
City | Dresden |
Country | Germany |