A design space exploration methodology for application specific MPSoC design
Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed › peer-review
Contributors
Abstract
System designers need to perform design-space exploration (DSE) to find appropriate number and type of processing elements (PEs) to be present in a Multiprocessor Systems-on-Chip (MPSoC) to support a throughput-constrained application. This paper presents a DSE methodology that provides application to MPSoC architecture mappings, where different PEs get used. The methodology starts from a mapping using only one type of processors and evaluates different mappings by increasing heterogeneity to improve the performance.
Details
Original language | English |
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Title of host publication | Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 |
Publisher | IEEE Xplore |
Pages | 339-340 |
Number of pages | 2 |
ISBN (electronic) | 978-0-7695-4447-2 (CD) |
ISBN (print) | 978-1-4577-0803-9 |
Publication status | Published - 2011 |
Peer-reviewed | Yes |
Externally published | Yes |
Publication series
Series | IEEE Computer Society Annual Symposium on VLSI |
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Conference
Title | 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 |
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Duration | 4 - 6 July 2011 |
City | Chennai |
Country | India |