A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in80nm CMOS

Research output: Contribution to book/conference proceedings/anthology/reportConference contributionContributedpeer-review

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Original languageEnglish
Title of host publicationSolid-State Circuits, 2006 IEEE International Conference Digest ofTechnical Papers
Pages2462-2471
Number of pages10
Publication statusPublished - 1 Feb 2006
Peer-reviewedYes

Keywords