This paper studies the design and measurement of a PAM-8 modulator driver based on a 3-bit digital-to-analog converter (DAC) architecture in a 130-nm SiGe BiCMOS process. The driver is implemented as a two-stage topology. The first stage consists of three single-ended to differential converters (SDC) and the second stage includes the DAC core. The driver has an output voltage swing of 4 Vpp.ditf, thus enabling high extinction ratios when implemented in an electro-optical transmitter. It reaches a symbol rate of 50 Gbaud and consumes 590 mW of DC power, therefore being one of the most power efficient drivers reported in the literature.