This letter presents the design of a 64-GHz power amplifier (PA) in a 22-nm FD-SOI CMOS technology. Benefiting from optimized pseudodifferential cascode gain cells as well as the alternate-layer stacked transformers for impedance matching and power combining, the two-stage PA delivers 21 dBm of output power from a 2-V supply voltage at a PAE of 28.7 %. Thanks to the low-loss 2:1 interstage matching transformer, the PA delivers 31 dB of power gain from a compact active area of 270 μ m × 124 μ m = 0.0335 mm2. To the best of our knowledge, the proposed PA has the highest output power to area ratio (Psat/Area) in comparison to the state of the art above 60 GHz.