0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Digital LDO is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-μA quiescent current at 200-μA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.
Details
| Original language | English |
|---|---|
| Title of host publication | IEEE Custom Integrated Circuits Conference 2010 |
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Pages | 1-4 |
| Number of pages | 4 |
| ISBN (print) | 978-1-4244-5759-5 |
| Publication status | Published - 22 Sept 2010 |
| Peer-reviewed | Yes |
Conference
| Title | IEEE Custom Integrated Circuits Conference 2010 |
|---|---|
| Duration | 19 - 22 September 2010 |
| Location | San Jose, CA, USA |
External IDs
| Scopus | 78649818058 |
|---|---|
| ORCID | /0000-0002-4152-1203/work/165453406 |
Keywords
Sustainable Development Goals
Keywords
- Clocks, Switches, Shift registers, CMOS integrated circuits, Bidirectional control, Transient analysis, Current measurement