Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits.

Publikation: Beitrag in FachzeitschriftForschungsartikelBeigetragenBegutachtung

Abstract

Individual transistors based on emerging reconfigurable nanotechnologies exhibit electrical conduction for both types of charge carriers. These transistors (referred to as Reconfigurable Field-Effect Transistors (RFETs)) enable dynamic reconfiguration to demonstrate either a p-or an n-type functionality. This duality of functionality at the transistor level is efficiently abstracted as a self-dual Boolean logic, that can be physically realized with fewer RFET transistors compared to the contemporary CMOS technology. Consequently, to achieve better area reduction for RFET-based circuits, the self-duality of a given circuit should be preserved during logic optimization and technology mapping. In this paper, we specifically aim to preserve self-duality by using Xor-Majority Graphs (XMGs) as the logic representation during logic synthesis and technology mapping. We propose a synthesis flow that uses new restructuring techniques, called rewriting and resubstitution for XMGs to preserve self-duality during technology-independent logic synthesis. For technology mapping, we use a novel open-source and a logic-representation agnostic mapping tool. Using the above-proposed XMG-based flow, we demonstrate its benefits by comparing post-mapping area for synthetic and cryptographic benchmarks with three different synthesis flows: (i) AIG-based optimization and AIG-based mapping; (ii) XMG-based optimization with AIG-based mapping; (iii) AIG-based optimization with logic-representation agnostic mapping. Our experiments show that the proposed XMG-based flow efficiently preserves self-duality and achieves the best area results for RFET-based circuits (up to 12.36% area reduction) with respect to the baseline.

Details

OriginalspracheEnglisch
Seiten (von - bis)914-927
Seitenumfang14
FachzeitschriftIEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jahrgang42
Ausgabenummer3
PublikationsstatusVeröffentlicht - 2023
Peer-Review-StatusJa

Externe IDs

Mendeley 9b3ffab9-b292-3728-9d11-76e98be1371c
Scopus 85134031657

Schlagworte

Forschungsprofillinien der TU Dresden

Schlagwörter

  • Benchmark testing, Logic gates, Nanoscale devices, Optimization, Runtime, Silicon, Transistors

Bibliotheksschlagworte