The Operating System of the Neuromorphic BrainScaleS-1 System

Publikation: Beitrag in FachzeitschriftForschungsartikelBeigetragenBegutachtung

Beitragende

  • Eric Müller - , Universität Heidelberg (Autor:in)
  • Sebastian Schmitt - , Georg-August-Universität Göttingen (Autor:in)
  • Christian Mauch - , Universität Heidelberg (Autor:in)
  • Sebastian Billaudelle - , Universität Heidelberg (Autor:in)
  • Andreas Grübl - , Universität Heidelberg (Autor:in)
  • Maurice Güttler - , Universität Heidelberg (Autor:in)
  • Dan Husmann - , Universität Heidelberg (Autor:in)
  • Joscha Ilmberger - , Universität Heidelberg (Autor:in)
  • Sebastian Jeltsch - , Universität Heidelberg (Autor:in)
  • Jakob Kaiser - , Universität Heidelberg (Autor:in)
  • Johann Klähn - , Universität Heidelberg (Autor:in)
  • Mitja Kleider - , Universität Heidelberg (Autor:in)
  • Christoph Koke - , Universität Heidelberg (Autor:in)
  • José Montes - , Universität Heidelberg (Autor:in)
  • Paul Müller - , Universität Heidelberg (Autor:in)
  • Johannes Partzsch - , Professur für Hochparallele VLSI-Systeme und Neuromikroelektronik (Autor:in)
  • Felix Passenberg - , Universität Heidelberg (Autor:in)
  • Hartmut Schmidt - , Universität Heidelberg (Autor:in)
  • Bernhard Vogginger - , Professur für Hochparallele VLSI-Systeme und Neuromikroelektronik (Autor:in)
  • Jonas Weidner - , Universität Heidelberg (Autor:in)
  • Christian Mayr - , Professur für Hochparallele VLSI-Systeme und Neuromikroelektronik (Autor:in)
  • Johannes Schemmel - , Universität Heidelberg (Autor:in)

Abstract

BrainScaleS-1 is a wafer-scale mixed-signal accelerated neuromorphic system targeted for research in the fields of computational neuroscience and beyond-von-Neumann computing. Here we present the BrainScaleS Operating System (BrainScaleS OS): the software stack gives users the possibility to emulate networks described in the high-level network description language PyNN with minimal knowledge of the system, as well as expert usage facilitated by allowing access to the system at any depth of the stack. BrainScaleS OS has been used extensively in the commissioning and calibration of BrainScaleS-1 as well as in various neuromorphic experiments, e.g., rate-based deep learning, accelerated physical emulation of Bayesian inference, solving of SAT problems, and others. The tolerance to faults of individual components of the neuromorphic system is reflected in the mapping process based on information stored in an availability database. We evaluate the robustness and compensation mechanisms of the system and software stack. The software stack is designed with performance in mind, with its core implemented in C++ and most user-facing API wrapped automatically to Python. The implemented multi-FPGA orchestration allows for parallel configuration and synchronized experiments facilitating wafer-scale experiments. The initial configuration of a wafer-scale experiment with hundreds of neuromorphic ASICs is performed in a fraction of a minute. Subsequent experiments, that potentially change only a subset of parameters, can be executed with rates of typically 10Hz. The bandwidth from the host machine to the neuromorphic system is fully utilized starting from a quarter of the system’s FPGA count. Operation and development methodologies implemented for the BrainScaleS-1 neuromorphic architecture are presented and the individual components of BrainScaleS OS constituting the software stack for BrainScaleS-1 platform operation are detailed.

Details

OriginalspracheEnglisch
Seiten (von - bis)790-810
Seitenumfang21
FachzeitschriftNeurocomputing
Jahrgang501
PublikationsstatusVeröffentlicht - 28 Aug. 2022
Peer-Review-StatusJa

Externe IDs

Scopus 85133220321
ORCID /0000-0002-6286-5064/work/142240641

Schlagworte

Schlagwörter

  • Neuromorphic computing, hardware abstraction, neuroscientific modeling, Neuroscientific modeling, Hardware abstraction