SoC compatible 1 T1 C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

  • Jun Okuno - , Sony Group Corporation (Autor:in)
  • Takafumi Kunihiro - , Sony Group Corporation (Autor:in)
  • Kenta Konishi - , Sony Group Corporation (Autor:in)
  • Hideki Maemura - , Sony Group Corporation (Autor:in)
  • Yusuke Shute - , Sony Group Corporation (Autor:in)
  • Fumitaka Sugaya - , Sony Group Corporation (Autor:in)
  • Monica Materano - , Professur für Nanoelektronik, Technische Universität Dresden (Autor:in)
  • Tarek Ali - , Fraunhofer-Institut für Photonische Mikrosysteme (Autor:in)
  • Kati Kuehnel - , Fraunhofer-Institut für Photonische Mikrosysteme (Autor:in)
  • Konrad Seide - , Fraunhofer-Institut für Photonische Mikrosysteme (Autor:in)
  • Uwe Schroeder - , Technische Universität Dresden (Autor:in)
  • Thomas Mikolajick - , Professur für Nanoelektronik, Technische Universität Dresden (Autor:in)
  • Masanori Tsukamoto - , Sony Group Corporation (Autor:in)
  • Taku Umebayashi - , Sony Group Corporation (Autor:in)

Abstract

This paper experimentally demonstrates fundamental memory array operation of a ferroelectric HfO2-based 1 T1 C FeRAM. Metal/ferroelectric/metal (MFM) capacitors consisting of a TiN/ Hf0.5Zr0.5O2(HZO)/TiN stack were optimized for a sub 500°C process. Structures revealed excellent performance such as remanent polarization 2Pr > 4\vert uC/cm2, endurance> 1011 cycles, and 10 years data retention at 85°C. Furthermore, the MFM capacitors were successfully integrated into a 64 kbit 1T1C FeRAM array including our dedicated circuit for array operation. Back-end-of-line (BEOL) wiring showed no degradation of the underlying CMOS logic. Program and read operation were properly controlled resulting in 100 % bit functionality at an operation voltage of2.5 Vand operating speed at 14 ns. This technology matches requirements of last level cash (LLC) and embedded non-volatile-memory (NVM) in low power System-on-a-Chip (SoC) for IoT applications.

Details

OriginalspracheEnglisch
Titel2020 IEEE Symposium on VLSI Technology
ErscheinungsortHonolulu
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers (IEEE)
ISBN (elektronisch)978-1-7281-6460-1
ISBN (Print)978-1-7281-6461-8
PublikationsstatusVeröffentlicht - Juni 2020
Peer-Review-StatusJa

Publikationsreihe

ReiheSymposium on VLSI Technology
Band2020-June
ISSN0743-1562

Konferenz

Titel2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020
Dauer16 - 19 Juni 2020
StadtHonolulu
LandUSA/Vereinigte Staaten

Externe IDs

ORCID /0000-0003-3814-0378/work/142256192

Schlagworte

ASJC Scopus Sachgebiete

Schlagwörter

  • capacitor, hafnium oxide, zirconium oxide