Simulation-based Evaluation of Lot Release Policies in a Power Semiconductor Facility - A Case Study

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

Abstract

Lot release policies, i.e., the decision which lots to start in production, in what quantity and at what time, have a significant influence on fab performance. Recent research focused on closed-loop policies. However, most studies only demonstrated the feasibility in settings with low-mix or low-volume simulation testbeds. In this paper, we focus on a real-world pre-assembly facility in a high-volume and high-mix semiconductor wafer fab. We conduct an in-depth, deterministic discrete-event simulation in two stages, using real production data and demands. First, we test two existing open-loop lot release policies (random and constant release) against a simple closed-loop release policy. Significant improvements in on-time delivery, bottleneck utilization, and throughput are notable. Second, we compare three closed-loop release policies and indicate which policy provides the best results for certain KPIs like enhanced on-time delivery or reduced tardiness.

Details

OriginalspracheEnglisch
TitelProceedings of the 2020 Winter Simulation Conference
ErscheinungsortPiscataway, NJ, USA
Herausgeber (Verlag)Wiley-IEEE Press
Seiten1503-1514
ISBN (elektronisch)978-1-7281-9499-8
PublikationsstatusVeröffentlicht - Dez. 2020
Peer-Review-StatusJa

Externe IDs

Scopus 85103889416
ORCID /0000-0002-3197-6159/work/142235848
ORCID /0000-0002-3549-080X/work/142245949
ORCID /0000-0001-6942-3763/work/142252882

Schlagworte

Schlagwörter

  • Semiconductor, manufacturing, optimization, AnyLogic, discrete event simulation, DOE, supply chain, logistics