Vertical silicon nanowire transistors are among the most promising device concepts for future low-power electronics due to their gate-all-around nature as well as their 3D stacking potential. In this work we review the current status of transistor fabrication on vertical silicon nanostructures and identify the most important challenges for successful process integration. Channel patterning, source/drain contact formation, gate-deposition and spacer engineering are identified as key steps independent on the actual process integration sequence. We conclude the paper with two emerging device examples and discuss the influence of the processing challenges on the transistor design.