Future chip technologies will change the way we deal with hardware design. First of all, logic resources will be available in vast amount. Furthermore, engineering specialized designs for particular applications will no longer be the general approach as the non recurring expenses will grow tremendously. Reconfigurable logic in the form of FPGAs and CGRAs has often been promoted as a solution to these problems. We believe that online synthesis that takes place during the execution of an application is one way to broaden the applicability of reconfigurable architectures as no expert knowledge of synthesis and technologies is required. In this paper we show that even a moderate amount of reconfigurable resources is sufficient to speed up applications considerably.