The vertical assembly between chip and interposer (2.5D) is mainly done by micro interconnects based on Cu pillars (diameter <50 μm, height <75 μm). These are typically manufactured via electroplating, which includes the sequential deposition of the Cu pillar itself and its solder cap (typically SnAg or Sn). In order to improve the yield of the subsequent assembly process as well as the overall reliability of these interconnects it is crucial to obtain information about their post process characteristics such as geometry (e.g. height and diameter, as well variations over the whole Si wafer), roughness, undercut, contamination level etc. Therefore it is important to introduce reliable metrology tools for wafer processing control. This study provides a detailed overview on important pillar characteristics and possible metrology solutions for their measurement, ranging from destructive failure analysis to promising in-line techniques. Furthermore, challenges and limits of the found solutions for various important pillar characteristics will be discussed. Derived from the provided overview on Cu pillar characteristics, this study will focus in detail on the measurement of the pillar sidewall loss and its roughness, the pillar undercut, the roughness of the insulator layer surrounding the pillar and the bottom critical dimension (CD). The sidewall parameters and the undercut of the pillar are difficult to characterize because of the geometrical arrangement and the associated inaccessibility by common measurement techniques (e.g. optical widefleld microscopy). The application of confocal microscopy with high resolution will be described in detail which enabled successful measurements of most of the described parameters (except undercut). The results will be discussed in terms of applicability for even smaller pillars (down to 25 μm) and in-line metrology capabilities.