Scaling options for S/D extension junctions of MOS transistors by anneal temperature variation or by application of co-implantation were investigated. Blank wafer and test structure experiments showed that the main contribution to reduce junction depth and to fulfill the requirements of downscaled devices was temperature reduction. The implementation of co-implantation of F, C or N or of pre-amorphization provided another degree of junction depth variation. For p⁺n-junctions suppression of B diffusion was found from SIMS measurements when the parameters of the co-implantation were optimized to the dopant implantation. Also the use of different species for pre-amorphization influenced the electrical junction characteristics, shown by SRP. For As implanted n⁺p-junctions a variation in electrical junction depth was observed that is related to the species implanted prior to the As dopant implantation.