This study investigates the role of the electrical failure of the SiO₂ film in the breakdown of SiO₂/ZrO₂ and SiO₂/HfO₂ stacks. Our findings indicate that the breakdown is governed by the SiO₂ film, regardless of its thickness. This highlights the importance of carefully considering the interfacial SiO₂ layer when using high-k materials in SiC devices. We demonstrate that thicker SiO₂ layers offer several benefits, including reduced leakage, enhanced thermal stability and electrical strength, and decreased trapping. In contrast, stacks with thinner SiO₂ have a higher effective k value, exploiting the benefits of high-k dielectrics. Our experimental results suggest that a 7 nm SiO₂ layer underlying 30 nm crystalline ZrO₂ or HfO₂ provides optimal performance. Furthermore, we present calculations that reveal the trade-off between SiO₂ thickness, k value, and breakdown voltage for a 50 nm thick dielectric stack. Our results imply that a k value exceeding 20 does not yield significant benefits in 50 nm thick SiO₂/dielectric stacks.