Ferroelectric field-effect transistors (FeFETs) based on ferroelectric (FE) HfO2 are raising strong interest as potential nonvolatile memory elements [1]. In a FeFET, the FE layer is integrated in the gate stack (Fig. 1) and the memory effect relies on its two stable polarization states ('up' and 'down'), which correspond to two distinct threshold voltage VT values (high- VT and low- VT state, respectively) of the transistor. While the initial assessment of a memory technology usually starts with considering single devices, the further optimization and qualification for memory applications requires the study of array structures. Single FeFETs often exhibit excellent switching performance and large memory window (MW) [2]. Nevertheless, FeFETs densely packed within arrays may present a noticeably lower performance, which is a consequence of a different electrical environment (write/read disturbs, different resistive and capacitive loads etc.) with respect to an isolated device.