Formal Analysis of Camouflaged Reconfigurable Circuits

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

Abstract

Reconfigurable field effect transistors are an emerging device technology. Reconfigurability between P-and N-type polarity and multiple (control) gates per device make them well suited for static and dynamic layout camouflaging as well as logic locking, watermarking and similar IP protection techniques. In contrast to classical transistors, the devices can provide fully symmetrical I-V characteristics between P-and N-type polarity with equal device geometry. In this paper, we explore logic gate variants and analyze their delay invariance using a fully automated design space exploration backed by probabilistic model checking. We evaluate how this invariance carries over to more complex combinational circuits and latches. Our analysis shows that effective camouflaging using reconfigurable logic gates is indeed achievable and identifies the most promising designs.

Details

OriginalspracheEnglisch
Titel2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers Inc.
ISBN (elektronisch)979-8-3503-0024-6
ISBN (Print)979-8-3503-0025-3
PublikationsstatusVeröffentlicht - 2023
Peer-Review-StatusJa

Publikationsreihe

ReiheAnnual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)
ISSN2472-467X

Konferenz

Titel21st IEEE Interregional NEWCAS Conference
KurztitelNEWCAS 2023
Veranstaltungsnummer21
Dauer26 - 28 Juni 2023
Webseite
BekanntheitsgradInternationale Veranstaltung
OrtJohn McIntyre Conference Centre
StadtEdinburgh
LandGroßbritannien/Vereinigtes Königreich

Externe IDs

ORCID /0000-0003-3814-0378/work/144255462

Schlagworte

Schlagwörter

  • Camouflaging, circuit analysis, device models, formal verification, reconfigurable logic, timing analysis