FAIL*: Towards a versatile fault-injection experiment framework

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

  • Horst Schirmeier - , Technische Universität (TU) Dortmund (Autor:in)
  • Martin Hoffmann - , Friedrich-Alexander-Universität Erlangen-Nürnberg (Autor:in)
  • Rüdiger Kapitza - , Technische Universität Braunschweig (Autor:in)
  • Daniel Lohmann - , Friedrich-Alexander-Universität Erlangen-Nürnberg (Autor:in)
  • Olaf Spinczyk - , Technische Universität (TU) Dortmund (Autor:in)

Abstract

Many years of research on dependable, fault-tolerant software systems yielded many tool implementations for vulnerability analysis and experimental validation of resilience measures. We identify two disjoint classes of fault-injection (FI) experiment tools in the field, and argue that both are plagued by inherent deficiencies, such as insufficient target state access, little or no means to switch to another target system, and non-reusable experiment code. In this article, we present a novel design approach for a FI infrastructure that aims at combining the strengths of both classes. Our Fail * experiment framework provides carefully-chosen abstractions simplifying both the implementation of different simulator/hardware target backends and the reuse of experiment code, while retaining the ability for deep targetstate access for specialized FI experiments. An exemplary report on first experiences with a prototype implementation based on existing x86 and ARM simulators demonstrates the tool's versatility.

Details

OriginalspracheEnglisch
TitelARCS Workshops, ARCS 2012
Herausgeber (Verlag)IEEE
Seiten1-5
Seitenumfang5
ISBN (elektronisch)978-3-88579-294-9
ISBN (Print)978-1-4673-1913-3
PublikationsstatusVeröffentlicht - 29 Feb. 2012
Peer-Review-StatusJa
Extern publiziertJa

Konferenz

Titel2012 International Conference on Architecture of Computing Systems, ARCS 2012
Dauer28 Februar - 2 März 2012
StadtMunchen
LandDeutschland

Externe IDs

Scopus 84864263013
ORCID /0000-0002-1427-9343/work/167216804

Schlagworte

Schlagwörter

  • Registers, Hardware, Prototypes, Computer architecture, Circuit faults, Software, IEEE Computer Society Press