Effect of independently sized gates on the delay of reconfigurable silicon nanowire transistor based circuits
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
Reconfigurable silicon nanowire field effect transistors (RFETs) provide both operation modes of p-type and n-type field effect transistors in a single multigate device. This unique feature provides additional degrees of freedom in terms of circuit design and device layout. Here a device-circuit co-design study of a novel 1-bit full adder with only 20 transistors is presented. The delay of the adder is analyzed using the logical effort theory and compared to standard CMOS implementation. The effect of independent gate sizing on device and circuit characteristics will be discussed. It will be shown that asymmetric gates can be exploited to reduce the critical delay of the new adder by 15 %, although the individual device performance is kept constant.
Details
Originalsprache | Englisch |
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Titel | EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon |
Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
Seiten | 17-20 |
Seitenumfang | 4 |
ISBN (elektronisch) | 9781479969111 |
Publikationsstatus | Veröffentlicht - 18 März 2015 |
Peer-Review-Status | Ja |
Publikationsreihe
Reihe | International Conference on Ultimate Integration of Silicon, ULIS |
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Konferenz
Titel | 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015 |
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Dauer | 26 - 28 Januar 2015 |
Stadt | Bologna |
Land | Italien |
Externe IDs
ORCID | /0000-0003-3814-0378/work/142256290 |
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Schlagworte
ASJC Scopus Sachgebiete
Schlagwörter
- device-circuit co-design, functional enhanced devices, logic gates, logical effort, multigate, polarity control, reconfigurable transistor, RFET, Schottky barrier, Schottky field effect transistor, silicon nanowires