The minimum operating voltage (VDDmin) of 90-nm CMOS ring oscillators (RO's) is investigated in order to clarify the lower limit of supply voltage (VDD) for logic circuits. The measured VDDmin is determined by the intra-die threshold voltage random variations and increased from 91 mV to 224 mV when the number of RO stages increased from 11 to 1001, which hinders the VDD scaling. Lowering VDDmin is difficult, since it would require an impractical inverter-by-inverter adaptive body bias control. Therefore, the fine-grain adaptive VDD control will be more effective for the ultra low voltage logic circuits to reduce the power consumption.