Continued transistor scaling and increasing power density has resulted in considerable increase in fault rates of nano-technology systems. Cross-layer fault tolerance techniques present a more cost-efficient methodology for adapting to such increased fault rates as opposed to fixing everything at the hardware layer. The effectiveness (Coverage, Fault-Masking and Recovery) and overheads (Execution time, Energy and Cost) of each fault tolerance technique varies with the layer and frequency at which it is applied. The choice of appropriate fault-aware design should also account for the application specific design goals and constraints of real-time systems. To this end, we provide a brief survey of fault-tolerance methods and discuss their suitability to cross-layer design. We also provide a few case studies that motivate the need for effective design space exploration (DSE) for cross-layer fault-aware design of real-time systems and discuss a few factors that have a major impact on such DSE.