The extended scalability of Twin Flash memory cells down to 32 nm half pitch is demonstrated in a conventional planar cell layout. Starting with 63 nm line space array and doubling the number of word lines, a cell size of 0.0112 μm² can be achieved. By dividing available space into 43 nm cell width and 20 nm space between adjacent cells the electrical cell characteristics could be maintained the same as in the previous 63 nm generation. It was found that the proposed aggressive shrinking of the cell spacing in word line direction results in a cross talk of 300 mV when both neighboring cells are programmed to the highest MLC level. The charge cross talk in charge trapping memory (CT) cells is reported for the first time and becomes an issue when cell spacing between Twin Flash and other CT cells as e.g. TANOS approaches the 20 nm mark.