An improved model for charge injection via inelastic tunneling in multilayer gate stacks is used to extract the trap distribution in the band gap of silicon nitride based nonvolatile memories. The new model allows the extraction of the trap distribution from program and discharge transients. We show that the trap distribution in the interface region of the gate stack has a large influence on the discharge behavior. The determined trap distribution is compared to the elastic TSCIS extraction method. Our model enables the simulation of discharge transients directly after program stress.