Analysis of Energy-Delay-Product of a 3D Vertical Nanowire FET Technology
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
To sustain transistor scaling beyond lateral 7nm devices, gate-all-around (GAA) junction-less vertical nanowire field effect transistors (VNWFET) are a promising alternative. This work analyses the energy-delay-product (EDP) for a junction-less 3D vertical gate-all-around nanowire FET technology, with a physical channel length of 14nm. Comparisons with the EDP of a baseline 7nm FinFET technology are carried out. The analysis motivates a new 3D neural network compute cube (N2C2) concept. Our results show that a 10x gain in EDP can be achieved for a physical VNWFET gate length of 14nm.
Details
| Originalsprache | Englisch |
|---|---|
| Titel | 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EuroSOI-ULIS 2021 |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers (IEEE) |
| Seiten | 1-4 |
| ISBN (elektronisch) | 978-1-6654-3745-5 |
| ISBN (Print) | 978-1-6654-3746-2 |
| Publikationsstatus | Veröffentlicht - 1 Sept. 2021 |
| Peer-Review-Status | Ja |
Publikationsreihe
| Reihe | International Conference on Ultimate Integration of Silicon, ULIS |
|---|---|
| ISSN | 2330-5738 |
Konferenz
| Titel | 7th Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon |
|---|---|
| Kurztitel | EuroSOI-ULIS 2021 |
| Veranstaltungsnummer | 7 |
| Dauer | 1 - 3 September 2021 |
| Webseite | |
| Ort | William the Conqueror Castel & Online |
| Stadt | Caen |
| Land | Frankreich |
Externe IDs
| ORCID | /0000-0003-3814-0378/work/142256172 |
|---|---|
| Scopus | 85118366515 |
Schlagworte
ASJC Scopus Sachgebiete
Schlagwörter
- logic circuit simulation, Vertical junctionless NWFET