A Mixed-Signal Offset-Compensation System for Multi-Gbit/s Optical Receiver Frontends

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Abstract

Offset compensation (OC) systems are indispensable parts of multi-Gbit/s optical receiver (RX) frontends. Effects of offset are addressed in this paper. The analytical expression for the highest lower-cut-off frequency of the OC with minimum impact on the sensitivity is found. Existing OC solutions are discussed. Then, a novel mixed-signal (MS) architecture is introduced which uses digital filtering of the signal, and current-digital-to-analog converters (IDACs) to compensate the static offset in the limiting amplifier (LA) and transimpedance amplifier (TIA), as well as continuously track and compensate the TIA offset. By using two feedback loops and a continuous tracking the presented solution offers more functionality than other existing MS architectures. Three RX implementations, with RC, switched-capacitor (S-C) and with the MS-OC architectures, in the same 28 nm bulk-CMOS are compared quantitatively with measurements. The presented MS design reaches a lower-cut-off frequency of under 9 kHz, a dynamic range of over 1 mA, 3. 2\muA residual input offset-current and it is compensating the RX via two feedback loops. These are achieved using an area of only 1345 \mu \mathrm{m}^{2}, nearly half of RC-filter based architecture. Although the SC implementation needs less area, its residual offset is 8 times higher. Both conventional implementations have a higher high-pass characteristic of about 20 kHz and can compensate only the offset of the TIA. It is concluded, that the presented system offers a higher flexibility and functionality in implementation, as well as a very good compromise between area, precision and performance over the commonly used RC-filter and S-C filter based solutions.

Details

OriginalspracheEnglisch
Titel27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Redakteure/-innenCarolina Metzler, Giovanni De Micheli, Pierre-Emmanuel Gaillardon, Carlos Silva-Cardenas, Ricardo Reis
Herausgeber (Verlag)IEEE Computer Society
Seiten46-51
Seitenumfang6
ISBN (elektronisch)9781728139159
PublikationsstatusVeröffentlicht - Okt. 2019
Peer-Review-StatusJa

Publikationsreihe

ReiheIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
Band2019-October
ISSN2324-8432

Konferenz

Titel2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration
KurztitelVLSI-SoC 2019
Veranstaltungsnummer27
Dauer6 - 9 Oktober 2019
StadtCuzco
LandPeru

Externe IDs

ORCID /0000-0002-1851-6828/work/142256633

Schlagworte

Forschungsprofillinien der TU Dresden

Schlagwörter

  • limiting amplifier (LA), lower-cut-off frequency, mixed-signal control loop, offset, offset compensation, Optical receiver, residual offset, transimpedance amplifier (TIA)