A design flow for partially reconfigurable heterogeneous multi-processor platforms
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
Modern multiprocessor systems-on-chip (MPSoCs) are expected to handle multi-application usecases. As the number and complexity of these applications scale, resource allocation to meet the application throughput requirement is becoming quite a challenge. In this paper, a complete design flow is proposed for partially reconfigurable heterogeneous MPSoC platforms. The proposed flow determines the minimum resources required to map and guarantee the throughput of applications in all use-cases. Further, a suitable mapping for each application is chosen so that energy consumption is minimized. Experiments conducted with a set of synthetic benchmarks and real-life applications clearly demonstrate the advantage of our approach over homogeneous or fully reconfigurable designs. The proposed design flow achieves more than 50% energy savings when the number of configurations is not optimized. With configuration-optimization, our flow results in 75% reduction in the number of configurations with 5% reduction in energy.
Details
Originalsprache | Englisch |
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Titel | Proceedings of the 2012 23rd IEEE International Symposium on Rapid System Prototyping |
Seiten | 170-176 |
Seitenumfang | 7 |
Publikationsstatus | Veröffentlicht - 2012 |
Peer-Review-Status | Ja |
Extern publiziert | Ja |
Publikationsreihe
Reihe | International Workshop on Rapid System Prototyping (RSP) |
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ISSN | 2150-5500 |
Konferenz
Titel | 23rd IEEE International Symposium on Rapid System Prototyping, RSP 2012 |
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Dauer | 11 - 12 Oktober 2012 |
Stadt | Tampere |
Land | Finnland |
Schlagworte
Forschungsprofillinien der TU Dresden
Ziele für nachhaltige Entwicklung
ASJC Scopus Sachgebiete
Schlagwörter
- Design-flow, Heterogeneous systems, Multiple use-cases, Partially reconfigurable systems