A sensor system for measuring the power-ground (PG) noise in very large scale integrated circuits is presented. The proposed system utilizes sensor elements with standard cell dimensions enabling high spatial resolution voltage measurements of power and ground rails. Asynchronous sub-sampling is used to directly convert the analog signals into the digital domain inside the sensors to ensure precise waveform acquisition. Timing signals are derived from a all-digital phase-locked-loop (ADPLL) which guarantees accurate low-noise sampling of the supply waveforms. The sensor system has been implemented in a 28nm CMOS test chip. Simultaneous acquisition of voltage drop and ground bounce at 300 probe points within a 120μm × 120μm macro at 62.5 ps time and up to 250μV voltage resolution shows the capabilities of both, high spatial and high temporal resolution measurement of PG noise.