An improved layout structure for current-steering (CS) digital-to-analog converters (DACs) is proposed which mitigates the frequency dependent signal degradations due to well-known parasitic capacitive effects. The presented structure is enabled by means of a comprehensive balanced clock and output network. As a proof-of-concept, a 1.6 GHz direct digital frequency synthesizer (DDFS) is presented comprising a 14 bit digital synthesis logic and a 12 bit current steering DAC. It is capable of producing sinusoidal waveforms with frequencies up to 800 MHz and a minimum frequency tuning step of 45.8 kHz. A high output power of 1.6 mW has been achieved at low power consumption of only 250 mW and a good spurious free dynamic range (SFDR) greater than 40 dBc.