A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS
Publikation: Beitrag in Fachzeitschrift › Forschungsartikel › Beigetragen › Begutachtung
Beitragende
Abstract
This paper presents a 0.6 V input, 0.3-0.55 V output buck converter in 40 nm CMOS, for low-voltage low-power wireless sensor network systems. A low power CCM/DCM controller of the buck converter enables automatic selection of DCM or CCM operation depending on load situation, therefore improving the power efficiency. A dual-mode-body-biased (DMBB) zero-crossing detector with both forward body bias mode and zero body bias mode is designed to enable DCM operation with both low supply voltage and normal supply voltage. An ultra-low-power hysteresis voltage detector is proposed for body bias modes selection. The proposed buck converter achieves a peak efficiency of 94% with an output current range of 50 μA to 10 mA. Thanks to the DCM operation, the efficiency at an output current of 10 μA is improved by 20% and 9%, with an output voltage of 0.35 V and 0.5 V, respectively.
Details
Originalsprache | Englisch |
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Aufsatznummer | 6872611 |
Seiten (von - bis) | 2377-2386 |
Seitenumfang | 10 |
Fachzeitschrift | IEEE journal of solid-state circuits |
Jahrgang | 49 |
Ausgabenummer | 11 |
Publikationsstatus | Veröffentlicht - 1 Nov. 2014 |
Peer-Review-Status | Ja |
Externe IDs
Scopus | 84908402477 |
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ORCID | /0000-0002-4152-1203/work/165453438 |
Schlagworte
Schlagwörter
- Detectors, Inductors, Clocks, Pulse width modulation, Delays, Voltage control, Logic gates