A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
A 0.5-V sigma-delta modulator implemented in a 0.15-mum FD-SOI process with low VTH of 0.1V using analog T-switch (AT-switch) scheme to suppress subthreshold-leakage problems is presented. The scheme is compared with the conventional circuit, which are also fabricated in the same chip. The measurement result demonstrates that the sigma-delta modulator based on AT-switch realizes 6-bit resolution through reducing nonlinear leakage effects while the conventional circuit can achieve 4-bit resolution
Details
Originalsprache | Englisch |
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Titel | Asia and South Pacific Conference on Design Automation, 2006. |
Herausgeber (Verlag) | IEEE |
ISBN (Print) | 0-7803-9451-8 |
Publikationsstatus | Veröffentlicht - 27 Jan. 2006 |
Peer-Review-Status | Ja |
Konferenz
Titel | Asia and South Pacific Conference on Design Automation, 2006. |
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Dauer | 24 - 27 Januar 2006 |
Ort | Yokohama, Japan |
Externe IDs
ORCID | /0000-0002-4152-1203/work/165453383 |
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Schlagworte
Schlagwörter
- Delta-sigma modulation, Subthreshold current, Variable structure systems, Very large scale integration, Semiconductor device measurement, Digital circuits, Threshold voltage, Logic, Analog circuits, Circuit synthesis