Each generation of the wireless communication networks has contiguous demands for higher computing capabilities and lower the power consumption in the integrated circuitry. Thus, the optimization of the base-band signal processing kernels and the hardware architectures plays a pivotal role in the performance, latency, and energy efficiency of the Physical Layer (PHY). Channel Estimation (CE), a computationally intensive task with hard real-time requirements, involves significant amounts of matrix multiplications and inversions, when data flows between transmitter (TX) and receiver (RX). In this work, we present a software implementation of CE for the 5th Generation Cellular Networks (5G) New Radio (NR) in the Reduced Instruction Set Computer (RISC)-V architecture, showcasing how its vector processing capabilities can satisfy the throughput and delay requirements of 5G use cases. Specifically, we ported two CE kernels, the Least-Squares (LSE) and Minimum Mean Square Error (MMSE), onto a state-of-the-art single core vector processor. By exploiting data vectorization, the ARA core computes matrix arithmetic operations on multiple data sets simultaneously. Our single vector core serial optimization demonstrates that with a 16× 16 matrix window size and 16 vector lanes, the application's performance achieves a speedup of 78.27 when computing the LSE algorithm. When the number of operations per cycle are compared, the vector processor outperforms its scalar counterpart by 181.91 for the MMSE kernel. Our implementation orders the nested loops in a latency-reducing fashion to compute matrix arithmetic operations, resulting in LSE and MMSE estimator computing times of 8.44 μiota s and 12.31 μs, respectively.