Reconfigurable Field-Effect Transistors are fully CMOS-compatible emerging devices capable of changing between n-type and p-type characteristics during runtime. This inherent polymorphism extends to the logic gate level, enabling circuit obfuscation beyond what can be achieved with traditional CMOS devices. In order to exploit these capabilities, especially for embedded security solutions at the edge, it is crucial that the devices operate at low voltages to minimize power consumption. This work presents the first demonstration of the highly expressive three-independent gate reconfigurable transistor variant operated at 0.8 V. The devices are processed based on the 22nm FDSOI technology of GlobalFoundries and are fully co-integratable with standard CMOS devices. We leverage the self-dual nature of these devices to implement a circuit obfuscation scheme to merge two individual circuits into a single one, thus illustrating a scalable method that can be extended to larger cryptographic engines to effectively mask their functionality from an outside attacker. The functionality of the method is validated by simulating a merged adder/subtractor circuit in Cadence Virtuoso, utilizing a previously developed Verilog-A model of the scaled devices. This work demonstrates the feasibility of RFETs operating at supply voltages as low as 0.8 V with symmetrical P and N on-states, enabling energy-efficient hardware security applications, such as reconfigurable adder/subtractor circuits and polymorphic logic blocks.